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5-65 st16c654/654d rev. 4.10 quad uart with 64-byte fifo and infrared (irda) encoder/decoder description the st16c654 * 1 is a universal asynchronous receiver and transmitter (uart) with a dual foot print interface compatible with the st16c554 and st68c554. the 654 is an enhanced uart with 64 byte fifos, automatic hardware/software flow control, and data rates up to 1.5mbps. onboard status registers provide the user with error indications and operational status, modem interface control. system interrupts may be tailored to meet user requirements. an internal loopback capability allows onboard diagnostics. the 654 is available in 64 pin tqfp, 68 pin plcc, and 100 pin qfp packages. the 64 pin package offers the 16 interface mode which is compatible with the industry standard st16c554. the 68 and 100 pin packages offer an additional 68 mode which allows easy integration with motorola, and other popular microprocessors. the st16c654cq64 (64 pin) offers three state interrupt control while the st16c654dcq64 provides constant active interrupt outputs. the 64 pin devices do not offer txrdy/rxrdy outputs or the default clock select option (clksel). the 100 pin packages offer faster channel status access by providing separate outputs for txrdy and rxrdy, offer separate infrared tx outputs and a musical instrument clock input (midiclk). the 654 combines the package interface modes of the 16c454/ 554 and 68/c454/554 series on a single integrated chip. part number pins package operating temperature st16c654ij68 68 plcc -40 c to + 85 c st16c654iq64 64 tqfp -40 c to + 85 c st16c654diq64 64 tqfp -40 c to + 85 c ST16C654IQ100 100 qfp -40 c to + 85 c note *1: patent pending features compatibility with the industry standard st16c454/554, st68c454/554, tl16c554 1.5 mbps transmit/receive operation (24mhz) 64 byte transmit fifo 64 byte receive fifo with error flags automatic software/hardware flow control programmable xon/xoff characters independent transmit and receive control software selectable baud rate generator pre- scaleable clock rates of 1x, 4x. four selectable transmit/receive fifo interrupt trigger levels standard modem interface or infrared irda en- coder/decoder interface software flow control turned off optionally by any (xon) rx character independent midi interface on 100 pin packages 100 pin packages offer internal register fifo monitoring and separate irda tx outputs sleep mode ( 200 m a stand-by) ordering information part number pins package operating temperature st16c654cj68 68 plcc 0 c to + 70 c st16c654cq64 64 tqfp 0 c to + 70 c st16c654dcq64 64 tqfp 0 c to + 70 c st16c654cq100 100 qfp 0 c to + 70 c plcc package 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb clksel 16/-68 a2 a1 a0 xtal1 xtal2 reset -rxrdy -txrdy gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -dsrc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd -rid -cdd st16c654cj68 16 mode
st16c654/654d 5-66 rev. 4.10 figure 1, package descriptions 100 pin qfp package 64 pin tqfp package 68 pin plcc package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 n.c. n.c. n.c. n.c. -txrdya irtxa -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb irtxb -txrdyb n.c. n.c. n.c. n.c. n.c. -rxrdyb -cdb -rib rxb clksel 16/-68 a2 a1 a0 xtal1 xtal2 midiclk reset -rxrdy -txrdy gnd rxc -ric -cdc -rxrdyc n.c. n.c. n.c. n.c. -csrdy irtxd -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -dsrc irtxc -txrdyc n.c. n.c. n.c. n.c. n.c. -rxrdya -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd -rid -cdd -rxrdyd -txrdyd st16c654cq100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow -txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc a2 a1 a0 xtal1 xtal2 reset gnd rxc -ric -cdc -dsrc -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 vcc rxd -rid -cdd st16c654cq64 st16c654dcq64 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa -irq -cs txa r/-w txb a3 n.c. -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb clksel 16/-68 a2 a1 a0 xtal1 xtal2 -reset -rxrdy -txrdy gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd n.c. n.c. txd n.c. txc a4 n.c. -rtsc vcc -dtrc -ctsc -dsrc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 n.c. vcc rxd -rid -cdd st16c654cj68 68 mode
st16c654/654d 5-67 rev. 4.10 figure 2, block diagram 16 mode d0-d7 -ior -iow reset a0-a2 -cs a-d int a-d -rxrdy -txrdy -rxrdy a-d -txrdy a-d intsel -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d rxir a-d xtal1 midi xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator ir encoder ir decoder
st16c654/654d 5-68 rev. 4.10 figure 3, block diagram 68 mode d0-d7 r/-w -reset a0-a4 -cs irq -rxrdy -txrdy -rxrdy a-d -txrdy a-d -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d irrx a-d xtal1 midi xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator ir encoder ir decoder
st16c654/654d 5-69 rev. 4.10 symbol description symbol pin signal pin description 68 100 64 type 16/-68 31 36 - i 16/68 interface type select (input with internal pull-up). - this input provides the 16 (intel) or 68 (motorola) bus interface type select. the functions of -ior, -iow, int a- d, and -cs a-d are re-assigned with the logical state of this pin. when this pin is a logic 1, the 16 mode interface 16c554 is selected. when this pin is a logic 0, the 68 mode interface (68c554) is selected. when this pin is a logic 0, -iow is re- assigned to r/-w, reset is re-assigned to -reset, -ior is not used, and int a-d(s) are connected in a wire-or configuration. the wire-or outputs are connected inter- nally to the open source irq signal output. this pin is not available on 64 pin packages which operate in the 16 mode only. a0 34 39 24 i address-0 select bit. internal registers address selection in 16 and 68 modes. a1 33 38 23 i address-1 select bit. internal registers address selection in 16 and 68 modes. a2 32 37 22 i address-2 select bit. - internal registers address selection in 16 and 68 modes. a3-a4 20,50 17,64 - i address 3-4 select bits. - when the 68 mode is selected, these pins are used to address or select individual uarts (providing -cs is a logic 0). in the 16 mode, these pins are reassigned as chip selects, see -csb and -csc. these pins are not available on 64 pin packages which operate in the 16 mode only. clksel 30 35 - i clock select. - the 1x or 4x pre-scaleable clock is selected by this pin. the 1x clock is selected when clksel is a logic 1 (connected to vcc) or the 4x is selected when clksel is a logic 0 (connected to gnd). mcr bit-7 can override the state of this pin following reset or initialization (see mcr bit- 7). this pin is not available on 64 pin packages which provide mcr bit-7 selection only. -cs 16 13 - i chip select. (active low) - in the 68 mode, this pin functions as a multiple channel chip enable. in this case, all four
st16c654/654d 5-70 rev. 4.10 symbol description uarts (a-d) are enabled when the -cs pin is a logic 0. an individual uart channel is selected by the data contents of address bits a3-a4. when the 16 mode is selected (68/100 pin devices), this pin functions as -csa, see definition under -cs a-b. this pin is not available on 64 pin packages which operate in the 16 mode only. -cs a-b 16,20 13,17 7,11 -cs c-d 50,54 64,68 38,42 i chip select a, b, c, d (active low) - this function is associated with the 16 mode only, and for individual chan- nels, a through d. when in 16 mode, these pins enable data transfers between the user cpu and the st16c654 for the channel(s) addressed. individual uart sections (a, b, c, d) are addressed by providing a logic 0 on the respective -cs a-d pin. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are de- scribed under the their respective name/pin headings. -csrdy - 76 - i control status ready (active low) - this feature is available on 100 pin qfp packages only. on 100 pin packages, the contents of the fifordy register is read when this pin is a logic 0. however it should be noted, d0-d3 will contain the inverted logic states of txrdy, status bits a-d, and d4-d7 the inverted logic states of rxrdy, status bits d4-d7. d0-d2 66-68 88-90 53-55 i/o d3-d7 1-5 91-95 56-60 data bus (bi-directional) - these pins are the eight bit, three state data bus for transferring information to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. gnd 6,23 96,20 14,28 gnd 40,57 46,71 45,61 pwr signal and power ground. int a-b 15,21 12,18 6,12 int c-d 49,55 63,69 37,43 o interrupt a, b, c, d (active high) - this function is associated with the 16 mode only. these pins provide individual channel interrupts, int a-d. int a-d are enabled when mcr bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (ier), and when an interrupt con- symbol pin signal pin description 68 100 64 type
st16c654/654d 5-71 rev. 4.10 symbol description dition exists. interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. intsel 65 87 - i interrupt select. (active high, with internal pull-down) - this function is associated with the 16 mode only. when the 16 mode is selected, this pin can be used in conjunction with mcr bit-3 to enable or disable the three state interrupts, int a-d or override mcr bit-3 and force continuous interrupts. interrupt outputs are enabled continuously by making this pin a logic 1. making this pin a logic 0 allows mcr bit-3 to control the three state interrupt output. in this mode, mcr bit-3 is set to a logic 1 to enable the three state outputs. this pin is disabled in the 68 mode. due to pin limitations on 64 pin packages, this pin is not available. to cover this limitation, two 64 pin qfp package versions are offered. the st16c654dcq64 operates in the continuos interrupt enable mode by bonded this pin to vcc internally. the st16c654cq64 operates with mcr bit-3 control by bond- ing this pin to gnd. -ior 52 66 40 i input/output read. (active low strobe) - this function is associated with the 16 mode only. a logic 0 transition on this pin will load the contents of an internal register defined by address bits a0-a2 onto the st16c654 data bus (d0-d7) for access by an external cpu. this pin is disabled in the 68 mode. -iow 18 15 9 i input/output write. (active low strobe) - this function is associated with the 16 mode only. a logic 0 transition on this pin will transfer the contents of the data bus (d0-d7) from the external cpu to an internal register that is defined by address bits a0/a2. when the 16 mode is selected (68/100 pin devices), this pin functions as r/-w, see definition under r/w. -irq 15 12 - o interrupt request or interrupt a - this function is associ- symbol pin signal pin description 68 100 64 type
st16c654/654d 5-72 rev. 4.10 symbol description symbol pin signal pin description 68 100 64 type ated with the 68 mode only. in the 68 mode, interrupts from uart channels a-d are wire-ored internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using -cs and a3- a4. in the 68 mode an external pull-up resistor must be connected between this pin and vcc. the function of this pin changes to inta when operating in the 16 mode, see definition under inta. irtx a-b - 6,24 - irtx c-d - 57,75 - o infrared transmit data output (irda) - this function is associated with 100 pin packages only. these pins provide separate infrared irda tx outputs for uart channels (a- d). the serial infrared irtx data is transmitted via these pins with added start, stop and parity bits. the irtx signal will be a logic 0 during reset, idle (no data), or when the transmitter is disabled. mcr bit-6 selects the standard modem or infrared interface. midiclk - 42 - i midi (musical instrument digital interface) clock input - this function is associated with 100 pin packages only. rxc and txc can function as midi input/output ports when an external midi clock is provided at this pin. external clock or a crystal is connected to the xtal1/2 pins for normal operation (see xtal 1 & 2). -reset reset 37 43 27 i reset. - in the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see st16c654 external reset conditions for initial- ization details.) when 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -reset. r/-w 18 15 - i read/write strobe (active low) - this function is associated with the 68 mode only. this pin provides the combined
st16c654/654d 5-73 rev. 4.10 symbol description symbol pin signal pin description 68 100 64 type functions for read or write strobes. a logic 1 to 0 transition transfers the contents of the cpu data bus (d0-d7) to the register selected by -cs and a0-a4. similarly a logic 0 to 1 transition places the contents of a 654 register selected by -cs and a0-a4 on the data bus, d0-d7, for transfer to an external cpu. -rxrdy 38 44 - o receive ready (active low) - this function is associated with 68 and 100 pin packages only. -rxrdy contains the wire or-ed status of all four receive channel fifos, rxrdy a-d. a logic 0 indicates receive data ready status, i.e. the rhr is full or the fifo has one or more rx characters available for unloading. this pin goes to a logic 1 when the fifo/rhr is full or when there are no more characters available in either the fifo or rhr. the 100 pin chip-sets provide both the combined wire ored output and individual channel rxrdy-a-d outputs. rxrdy a-d is discussed in a following paragraph. for 64/68 pin packages, individual channel rx status is read by examining indi- vidual internal registers via -cs and a0-a4 pin functions. -rxrdy a-b - 100,31 -rxrdy c-d - 50,82 - o receive ready a-d (active low) - this function is associ- ated with 100 pin packages only. this function provides the rx fifo/rhr status for individual receive channels (a-d). a logic 0 indicates there is receive data to read/unload, i.e., receive ready status with one or more rx characters available in the fifo/rhr. this pin is a logic 1 when the fifo/rhr is empty or when the programmed trigger level has not been reached. -txrdy 39 45 - o (active low) - this function is associated with 68 and 100 pin packages only. -txrdy contains the wire or-ed status of all four transmit channel fifos, txrdy a-d. a logic 0 indicates a buffer ready status, i.e., at least one location is empty and available in one of the tx channels (a-d). this pin goes to a logic 1 when all four channels have no more empty locations in the tx fifo or thr. the 100 pin chip- sets provide both the combined wire ored output and individual channel txrdy-a-d outputs. txrdy a-d is
st16c654/654d 5-74 rev. 4.10 symbol pin signal pin description 68 100 64 type discussed in a following paragraph for 64/68 pin packages, individual channel tx status can be read by examining individual internal registers via -cs and a0-a4 pin func- tions. -txrdy a-b - 5,25 -txrdy c-d - 56,81 - o this function is associated with 100 pin packages only. these outputs provide the tx fifo/thr status for indi- vidual transmit channels (a-d). as such, an individual channels -txrdy a-d buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the fifo or thr. this pin goes to a logic 1 when there are no more empty locations in the fifo or thr. vcc 13 10 4,21 vcc 47,64 61,86 35,52 i power supply inputs. xtal1 35 40 25 i crystal or external clock input - functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit (see figure 8). alternatively, an external clock can be connected to this pin to provide custom data rates (see baud rate generator programming and optional midclk). xtal2 36 41 26 o output of the crystal oscillator or buffered clock - (see also xtal1). crystal oscillator output or buffered clock output. -cd a-b 9,27 99,32 64,18 -cd c-d 43,61 49,83 31,49 i carrier detect (active low) - these inputs are associated with individual uart channels a through d. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -cts a-b 11,25 8,22 2,16 -cts c-d 45,59 59,73 33,47 i clear to send (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on the - cts pin indicates the modem or data set is ready to accept transmit data from the 654. status can be tested by reading msr bit-4. this pin only affects the transmit and receive operations when auto cts function is enabled via the symbol description
st16c654/654d 5-75 rev. 4.10 symbol pin signal pin description 68 100 64 type enhanced feature register (efr) bit-7, for hardware flow control operation. -dsr a-b 10,26 7,23 1,17 -dsr c-d 44,60 58,74 32,48 i data set ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uarts transmit or receive operation. -dtr a-b 12,24 9,21 3,15 -dtr c-d 46,58 60,72 34,46 o data terminal ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates that the 654 is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr bit-0 will set the -dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr bit-0, or after a reset. this pin has no effect on the uarts transmit or receive opera- tion. -ri a-b 8,28 98,33 63,19 -ri c-d 42,62 48,84 30,50 i ring indicator (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. -rts a-b 14,22 11,19 5,13 -rts c-d 48,56 62,70 36,44 o request to send (active low) - these outputs are associated with individual uart channels, a through d. a logic 0 on the -rts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register (mcr bit-1) will set this pin to a logic 0 indicating data is available. after a reset this pin will be set to a logic 1. this pin only affects the transmit and receive operations when auto rts function is enabled via the enhanced feature register (efr) bit-6, for hardware flow control operation. symbol description
st16c654/654d 5-76 rev. 4.10 symbol pin signal pin description 68 100 64 type rx/irrx a-b 7,29 97,34 62,20 rx/irrx c-d 41,63 47,85 29,51 i receive data input rx/irrx a-d. - these inputs are associated with individual serial channel data to the st16c654. two user selectable interface options are avail- able. the first option supports the standard modem inter- face. the second option provides an infrared decoder interface, see figures 2/3. when using the standard modem interface, the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. the inactive state (no data) for the infrared decoder interface is a logic 0. mcr bit-6 selects the standard modem or infrared interface. during the local loopback mode, the rx input pin is disabled and tx data is internally connected to the uart rx input, internally. tx/irtx a-b 17,19 14,16 8,10 tx/irtx c-d 51,53 65,67 39,41 o transmit data - these outputs are associated with indi- vidual serial transmit channel data from the 654. two user selectable interface options are available. the first user option supports a standard modem interface. the second option provides an infrared encoder interface, see figures 2/ 3. when using the standard modem interface, the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. the inactive state (no data) for the infrared encoder/ decoder interface is a logic 0. mcr bit- 6 selects the standard modem or infrared interface. during the local loopback mode, the tx input pin is disabled and tx data is internally connected to the uart rx input. symbol description
st16c654/654d 5-77 rev. 4.10 general description the 654 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integ- rity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the st16c654 represents such an integration with greatly enhanced features. the 654 is fabricated with an advanced cmos process to achieve low drain power and high speed requirements. the 654 is an upward solution that provides 64 bytes of transmit and receive fifo memory, instead of 16 bytes provided in the 16/68c554, or none in the 16/ 68c454. the 654 is designed to work with high speed modems and shared network environments, that re- quire fast data processing time. increased perfor- mance is realized in the 654 by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. for example, the st16c554 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 64 byte fifo in the 654, the data buffer will not require unloading/loading for 6.1 ms. this increases the service interval giving the external cpu additional time for other applications and reduc- ing the overall uart interrupt servicing time. in addition, the 4 selectable levels of fifo trigger inter- rupt and automatic hardware/software flow control is uniquely provided for maximum data throughput per- formance especially when operating in a multi-chan- nel environment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the 654 combines the package interface modes of the 16c454/554 and 68/c454/554 series on a single inte- grated chip. the 16 mode interface is designed to operate with the intel type of microprocessor bus while the 68 mode is intended to operate with motorola, and other popular microprocessors. following a reset, the 654 is down-ward compatible with the st16c454/ st68c454 or the st68c454/st68c554 dependent on the state of the interface mode selection pin, 16/- 68. the 654 is capable of operation to 1.5mbps with a 24 mhz crystal or external clock input. with a crystal of 14.7464 mhz and through a software option, the user can select data rates up to 460.8kbps or 921.6kbps, 8 times faster than the 16c554. the rich feature set of the 654 is available through internal registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared encoder/decoder interface, modem interface con- trols, and a sleep mode are all standard features. mcr bit-5 provides a facility for turning off (xon) software flow control with any incoming (rx) character. in the 16 mode intsel and mcr bit-3 can be configured to provide a software controlled or continuous interrupt capability. due of pin limitations for the 64 pin 654 this feature is offered by two different qfp packages. the st16c654dcq64 operates in the continuos interrupt enable mode by bonded intsel to vcc internally. the st16c654cq64 operates in conjunction with mcr bit-3 by bonding intsel to gnd internally. the 68 and 100 pin st16c654 packages offer a clock select pin to allow system/board designers to preset the default baud rate table. the clksel pin selects the 1x or 4x pre-scaleable baud rate generator table during initialization, but can be overridden following initialization by mcr bit-7. the 100 pin packages offer several enhances fea- tures. these features include an midi clock input, an internal fifo monitor register, and separate irda tx outputs. the midi (musical instrument digital inter- face) can be connected to the xtal2 pin for normal
st16c654/654d 5-78 rev. 4.10 operation or to external midi oscillator for midi appli- cations. a separate register is provided for monitoring the realtime status of the fifo signals -txrdy and - rxrdy for each of the four uart channels (a-d). this reduces polling time involved in accessing indi- vidual channels. the 100 pin qfp package also offers, four separate irda (infrared data association standard) outputs for infrared applications. these outputs are provided in addition to the standard asyn- chronous modem data outputs. functional descriptions interface options two user interface modes are selectable for the 654 package. these interface modes are designated as the 16 mode and the 68 mode. this nomenclature corresponds to the early 16c454/554 and 68c454/ 554 package interfaces respectively. the 16 mode interface the 16 mode configures the package interface pins for connection as a standard 16 series (intel) device and operates similar to the standard cpu interface avail- able on the 16c454/554. in the 16 mode (pin 16/-68 logic 1) each uart is selected with individual chip select (csx) pins as shown in table 2 below. table 2, serial port channel selection guide, 16 mode interface -csa -csb -csc -csd uart channel 1111 none 0111 a 1011 b 1101 c 1110 d the 68 mode interface the 68 mode configures the package interface pins for connection with motorola, and other popular micro- processor bus types. the interface operates similar to the 68c454/554. in this mode the 654 decodes two additional addresses, a3-a4 to select one of the four uart ports. the a3-a4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in table 3 below. table 3, serial port channel selection guide, 68 mode interface -cs a4 a3 uart channel 1 n/a n/a none 000 a 001 b 010 c 011 d internal registers the 654 provides 15 (64/68 pin packages) or 16 (100 pin packages) internal registers for monitoring and control. these resisters are shown in table 4 below. twelve registers are similar to those already available in the standard 16c554. these registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control regis- ter (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), pro- grammable data rate (clock) control registers (dll/ dlm), and a user assessable scratchpad register (spr). beyond the general 16c554 features and capabilities, the 654 offers an enhanced feature reg- ister set (efr, xon/xoff 1-2) that provides on board hardware/software flow control. register functions are more fully described in the following paragraphs.
st16c654/654d 5-79 rev. 4.10 table 4, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register 1 0 0 modem control register 1 0 1 line status register 1 1 0 modem status register 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm): note *2 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch enhanced register set (efr, xon/off 1-2): note *3 0 1 0 enhanced feature register enhanced feature register 1 0 0 xon-1 word xon-1 word 1 0 1 xon-2 word xon-2 word 1 1 0 xoff-1 word xoff-1 word 1 1 1 xoff-2 word xoff-2 word fifo ready register: note *4 x x x rxrdy (a-d), txrdy (a-d) note *2: these registers are accessible only when lcr bit-7 is set to a logic 1. note *3: enhanced feature register, xon 1,2 and xoff 1,2 are accessible only when the lcr is set to bf(hex). note *4: fifo ready register is available through the csrdy interface pin only.
st16c654/654d 5-80 rev. 4.10 fifo operation the 64 byte transmit and receive data fifos are enabled by the fifo control register (fcr) bit-0. with 16c554 devices, the user can set the receive trigger level but not the transmit trigger level. the 654 provides independent trigger levels for both receiver and transmitter. to remain compatible with st16c554, the transmit interrupt trigger level is set to 8 following a reset. it should be noted that the user can set the transmit trigger levels by writing to the fcr register, but activation will not take place until efr bit- 4 is set to a logic 1. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing). hardware flow control when automatic hardware flow control is enabled, the 654 monitors the -cts pin for a remote buffer overflow indication and controls the -rts pin for local buffer overflows. automatic hardware flow control is se- lected by setting bits 6 (rts) and 7 (cts) of the efr register to a logic 1. if -cts transitions from a logic 0 to a logic 1 indicating a flow control request, isr bit- 5 will be set to a logic 1 (if enabled via ier bit 6-7), and the 654 will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the -cts input returns to a logic 0, indicating more data may be sent. with the auto rts function enabled, an interrupt is generated when the receive fifo reaches the pro- grammed trigger level. the -rts pin will not be forced to a logic 1 (rts off), until the receive fifo reaches the next trigger level . however, the -rts pin will return to a logic 0 after the data buffer (fifo) is unloaded to the next trigger level below the pro- grammed trigger. however, under the above de- scribed conditions the 654 will continue to accept data until the receive fifo is full. selected int -rts -rts trigger pin logic 1 logic 0 level activation (characters) (characters) (characters) 88 16 0 16 16 56 8 56 56 60 16 60 60 60 56
st16c654/654d 5-81 rev. 4.10 software flow control when software flow control is enabled, the 654 com- pares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) (rx) match the pro- grammed values, the 654 will halt transmission (tx) as soon as the current character(s) has completed transmission. when a match occurs, the receive ready (if enabled via xoff ier bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. following a suspension due to a match of the xoff characters values, the 654 will monitor the receive data stream for a match to the xon-1,2 character value(s). if a match is found, the 654 will resume operation and clear the flags (isr bit- 4). the 654 offers a special xon mode via mcr bit-5. the initialized default setting of mcr bit-5 is a logic 0. in this state xoff and xon will operate as defined above. setting mcr bit-5 to a logic 1 sets a special operational mode for the xon function. in this case xoff operates normally however, transmission (xon) will resume with the next character received, i.e., a match is declared simply by the receipt of an incoming (rx) character. reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow control. different conditions can be set to detect xon/xoff characters and suspend/resume transmis- sions. when double 8-bit xon/xoff characters are selected, the 654 compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmis- sions accordingly. under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 654 automati- cally sends an xoff message (when enabled) via the serial tx output to the remote modem. the 654 sends the xoff-1,2 characters as soon as received data passes the programmed trigger level. to clear this condition, the 654 will transmit the programmed xon- 1,2 characters as soon as receive data drops below the programmed trigger level. special feature software flow control a special feature is provided to detect an 8-bit charac- ter when bit-5 is set in the enhanced feature register (efr). when 8 bit character is detected, it will be placed on the user accessible data stack along with normal incoming rx data. this condition is selected in conjunction with efr bits 0-3. note that software flow control should be turned off when using this special mode by setting efr bit 0-3 to a logic 0. the 654 compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character (see figure 9). although the internal register table shows each x- register with eight bits of character information, the actual number of bits is dependent on the pro- grammed word length. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the x-registers corresponds with the lsb bit for the receive character. xon any feature a special feature is provided to return the xoff flow control to the inactive state following its activation. in this mode any rx character received will return the xoff flow control to the inactive state so that transmis- sions may be resumed with a remote buffer. this feature is more fully defined in the software flow control section. hardware/software and timeout interrupts three special interrupts have been added to monitor the hardware and software flow control. the interrupts are enabled by ier bits 5-7. care must be taken when handling these interrupts. following a reset the trans- mitter interrupt is enabled, the 654 will issue an interrupt to indicate that transmit holding register is empty. this interrupt must be serviced prior to con- tinuing operations. the lsr register provides the
st16c654/654d 5-82 rev. 4.10 current singular highest priority interrupt only. it could be noted that cts and rts interrupts have lowest interrupt priority. a condition can exist where a higher priority interrupt may mask the lower priority cts/ rts interrupt(s). only after servicing the higher pend- ing interrupt will the lower priority cts/ rts interrupt(s) be reflected in the status register. servic- ing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier bit-3). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case the 654 fifo may hold more characters than the programmed trigger level. follow- ing the removal of a data byte, the user should recheck lsr bit-0 for additional characters. a receive time out will not occur if the receive fifo is empty. the time out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time out value is t ( t ime out length in bits) = 4 x p ( p rogrammed word length) + 12. to convert the time out value to a character value, the user has to consider the complete word length, includ- ing data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. example -a: if the user programs a word length of 7, with no parity and one stop bit, the time out will be: t = 4 x 7( programmed word length) +12 = 40 bit times. the character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex- ample: t = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. example -b: if the user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bit times. character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. in the 16 mode for 68/100 pin packages, the system/ board designer can optionally provide software con- trolled three state interrupt operation. this is accom- plished by intsel and mcr bit-3. when intsel interface pin is left open or made a logic 0, mcr bit- 3 controls the three state interrupt outputs, int a-d. when intsel is a logic 1, mcr bit-3 has no effect on the int a-d outputs and the package operates with interrupt outputs enabled continuously. programmable baud rate generator the 654 supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example a 33.6kbps modem that employs data compression may require a 115.2kbps input data rate. a 128.0kbps isdn modem that supports data compression may need an input data rate of 460.8kbps. the 654 can support a stan- dard data rate of 921.6kbps. a dual baud rate generator is provided for the transmitter and receiver, allowing independent tx/ rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 24 mhz, as required for supporting a 1.5mbps data rate. the 654 can be configured for internal or external clock operation. for internal clock oscilla- tor operation, an industry standard microprocessor c1 22pf c2 33pf x1 1.8432 mhz xtal1 xtal2 figure 8, crystal oscillator connection
st16c654/654d 5-83 rev. 4.10 crystal (parallel resonant/ 22-33 pf load) is con- nected externally between the xtal1 and xtal2 pins (see figure ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. (see baud rate generator programming). the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the 654 divides the basic crystal or external clock by 16. further division of this 16x clock provides two table rates to support low and high data rate applications using the same system design. after a hardware reset and during initializa- tion, the 654 sets the default baud rate table according to the state of the clksel. pin. a logic 0 on clksel will set the 1x clock default whereas, a logic will set the 4x clock default table. following the default clock rate selection during initialization, the rate tables can be changed by the internal register, mcr bit-7. setting mcr bit-7 to a logic 1 when clksel is a logic 1 provides an additional divide by 4 whereas, setting mcr bit-7 to a logic 0 only divides by 1. (see table 5 and figure 11). customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired final baud rate. the example in table 5 below, shows the two selectable baud rate tables available when using a 7.3728 mhz crystal. table 5, baud rate generator programming table (7.3728 mhz clock): output output user user dlm dll baud rate baud rate 16 x clock 16 x clock program program mcr mcr divisor divisor value value bit-7=1 bit-7=0 (decimal) (hex) (hex) (hex) 50 200 2304 900 09 00 300 1200 384 180 01 80 600 2400 192 c0 00 c0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2k 24 18 00 18 9600 38.4k 12 0c 00 0c 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01
st16c654/654d 5-84 rev. 4.10 figure 11, baud rate generator circuitry divide by 1 logic x tal1 x tal2 divide by 4 logic clock oscillator logic baudrate generator logic -baudout mcr bit-7=0 mcr bit-7=1
st16c654/654d 5-85 rev. 4.10 dma operation the 654 fifo trigger level provides additional flexibil- ity to the user for block mode operation. lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr bit-3). when the transmit and receive fifos are enabled and the dma mode is deactivated (dma mode 0), the 654 activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode 1), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the preset trigger level. in this mode, the 654 sets the interrupt output pin when characters in the transmit fifos are below the transmit trigger level, or the characters in the receive fifos are above the receive trigger level. sleep mode the 654 is designed to operate with low power con- sumption. a special sleep mode is included to further reduce power consumption when the chip is not being used. with efr bit-4 and ier bit-4 enabled (set to a logic 1), the 654 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins rx, -ri, -cts, -dsr, -cd, or transmit data is provided by the user. if the sleep mode is enabled and the 654 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. in any case, the sleep mode will not be entered while an interrupt(s) is pending. the 654 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. loopback mode the internal loopback capability allows onboard diag- nostics. in the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally. mcr register bits 0-3 are used for controlling loopback diagnostic testing. in the loopback mode op1 and op2 in the mcr register (bits 3/2) control the modem -ri and -cd inputs respectively. mcr signals -dtr and -rts (bits 0-1) are used to control the modem -cts and -dsr inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their asso- ciated interface pins, and instead are connected to- gether internally (see figure 12). the -cts, -dsr, - cd, and -ri are disconnected from their normal modem control inputs pins, and instead are connected internally to -dtr, -rts, -op1 and -op2. loopback test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loopback connec- tion. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem control register (mcr bits 0-3) instead of the four modem status register bits 4-7. the interrupts are still con- trolled by the ier.
st16c654/654d 5-86 rev. 4.10 figure 12, internal loopback mode diagram d0-d7 -ior,-iow reset a0-a2 -cs a-d int a-d -rxrdy -txrdy tx a-d rx a-d data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 xtal2 ir encoder ir decoder -cts a-d -rts a-d -dtr a-d -dsr a-d -ri a-d -cd a-d -op1 a-d -op2 a-d mcr bit-4=1
st16c654/654d 5-87 rev. 4.10 register functional descriptions the following table delineates the assigned bit functions for the fifteen 654 internal registers. the assigned bit functions are more fully defined in the following paragraphs. table 6, st16c654 internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *5 general register set 0 0 0 rhr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier[00] cts rts xoff sleep modem receive transmit receive interrupt interrupt interrupt mode status line holding holding interrupt status register register interrupt 0 1 0 fcr rcvr rcvr tx tx dma xmit rcvr fifo trigger trigger trigger trigger mode fifo fifo enable (msb) (lsb) (msb) (lsb) select reset reset 0 1 0 isr[01] fifos fifos int int int int int int enabled enabled priority priority priority priority priority status bit-4 bit-3 bit-2 bit-1 bit-0 0 1 1 lcr[00] divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 mcr[00] clock ir xon loop -op2/ -op1 -rts -dtr select enable any back intx enable 1 0 1 lsr[60] fifo trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 msr[x0] cd ri dsr cts delta delta delta delta -cd -ri -dsr -cts 1 1 1 spr[ff] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 special register set: note *2 0 0 0 dll[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm[xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
st16c654/654d 5-88 rev. 4.10 a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [note *5] enhanced register set: note *3 0 1 0 efr[00] auto auto special enable cont-3 cont-2 cont-1 cont-0 cts rts char. ier tx,rx tx,rx tx,rx tx,rx select bits 4-7, control control control control isr, fcr bits 4-5, mcr bits 5-7 1 0 0 xon-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 1 1 0 xoff-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 fifo ready register: note *4 x x x fifordy rxrdy rxrdy rxrdy rxrdy txrdy txrdy txrdy txrdy dcbadcba note * 2 : the special register set is accessible only when lcr bit-7 is set to 1. note * 3 : enhanced feature register, xon 1,2 and xoff 1,2 are accessible only when lcr is set to bf hex note * 4 : fifordy register is available only in 100 pin qfp packages and is selected by -csrdy vice a0-a2. note * 5 : the value between the square brackets represents the registers initialized hex value.
st16c654/654d 5-89 rev. 4.10 transmit (thr) and receive (rhr) holding reg- isters the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = fifo full, logic 1= at least one fifo location available). the serial receive section also contains an 8-bit receive holding register, rhr. receive data is removed from the 654 and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assem- bling a false character. receiver status codes will be posted in the lsr. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the int a-d output pins in the 16 mode, or on wire-or irq output pin, in the 68 mode. ier vs receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: a) the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b) fifo status will also be reflected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c) the data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. ier vs receive/transmit fifo polled mode op- eration when fcr bit-0 equals a logic 1; resetting ier bits 0-3 enables the 654 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a) lsr bit-0 will be a logic 1 as long as there is one byte in the receive fifo. b) lsr bit 1-4 will provide the type of errors encoun- tered, if any. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both the transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate any fifo data errors. ier bit-0: this interrupt will be issued when the fifo has reached the programmed trigger level or is cleared when the fifo drops below the trigger level in the fifo mode of operation. logic 0 = disable the receiver ready interrupt. (normal default condition) logic 1 = enable the receiver ready interrupt. ier bit-1: this interrupt will be issued whenever the thr is empty and is associated with bit-1 in the lsr register.
st16c654/654d 5-90 rev. 4.10 logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. ier bit-2: this interrupt will be issued whenever a fully as- sembled receive character is transferred from the rsr to the rhr/fifo, i.e., data ready, lsr bit-0. logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt. ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. ier bit -4: logic 0 = disable sleep mode. (normal default condi- tion) logic 1 = enable sleep mode. see sleep mode section for details. ier bit-5: logic 0 = disable the software flow control, receive xoff interrupt. (normal default condition) logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier bit-6: logic 0 = disable the rts interrupt. (normal default condition) logic 1 = enable the rts interrupt. the 654 issues an interrupt when the rts pin transitions from a logic 0 to a logic 1. ier bit-7: logic 0 = disable the cts interrupt. (normal default condition) logic 1 = enable the cts interrupt. the 654 issues an interrupt when cts pin transitions from a logic 0 to a logic 1. fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: dma mode mode 0 set and enable the interrupt for each single transmit or receive operation, and is similar to the st16c454 mode. transmit ready (-txrdy) will go to a logic 0 when ever an empty transmit space is available in the transmit holding register (thr). receive ready (-rxrdy) will go to a logic 0 when- ever the receive holding register (rhr) is loaded with a character. mode 1 set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo is below the programmed trigger level. -txrdy remains a logic 0 as long as one empty fifo location is available. the receive interrupt is set when the receive fifo fills to the programmed trigger level. however the fifo continues to fill regardless of the programmed level until the fifo is full. -rxrdy remains a logic 0 as long as the fifo fill level is above the programmed trigger level. fcr bit-0: logic 0 = disable the transmit and receive fifo. (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to or they will not be programmed. fcr bit-1: logic 0 = no fifo receive reset. (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-2: logic 0 = no fifo transmit reset. (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-3: logic 0 = set dma mode 0. (normal default condi- tion) logic 1 = set dma mode 1.
st16c654/654d 5-91 rev. 4.10 transmit operation in mode 0: when the 654 is in the st16c450 mode (fifos disabled, fcr bit-0 = logic 0) or in the fifo mode (fifos enabled, fcr bit-0 = logic 1, fcr bit-3 = logic 0) and when there are no characters in the transmit fifo or transmit holding register, the -txrdy pin will be a logic 0. once active the -txrdy pin will go to a logic 1 after the first character is loaded into the transmit holding register. receive operation in mode 0: when the 654 is in mode 0 (fcr bit-0 = logic 0) or in the fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 0) and there is at least one character in the receive fifo, the -rxrdy pin will be a logic 0. once active the -rxrdy pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode 1: when the 654 is in fifo mode ( fcr bit-0 = logic 1, fcr bit-3 = logic 1 ), the -txrdy pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode 1: when the 654 is in fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 1) and the trigger level has been reached, or a receive time out has occurred, the - rxrdy pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. fcr bit 4-5: (logic 0 or cleared is the default condi- tion, tx trigger level = 8) these bits are used to set the trigger level for the transmit fifo interrupt. the st16c654 will issue a transmit empty interrupt when the number of charac- ters in fifo drops below the selected trigger level. bit-5 bit-4 tx fifo trigger level 00 8 01 16 10 32 11 56 fcr bit 6-7: (logic 0 or cleared is the default condi- tion, rx trigger level = 8) these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of charac- ters in the fifo equals the programmed trigger level. however the fifo will continue to be loaded until it is full. bit-7 bit-6 rx fifo trigger level 00 8 01 16 10 56 11 60 interrupt status register (isr) the 654 provides six levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six inter- rupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowl- edged until the pending interrupt is serviced. when- ever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after rereading the interrupt status bits. the interrupt source table 7 (below) shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:
st16c654/654d 5-92 rev. 4.10 table 7, interrupt source table priority [ isr bits ] level bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 source of the interrupt 1 000110 lsr (receiver line status register) 2 000100 rxrdy (received data ready) 2 001100 rxrdy (receive data time out) 3 000010 txrdy ( transmitter holding register empty) 4 000000 msr (modem status register) 5 010000 rxrdy (received xoff signal)/ special character 6 100000 cts, rts change of state isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condi- tion) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-5: (logic 0 or cleared is the default condition) these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that matching xoff character(s) have been detected. isr bit-5 indicates that cts, rts have been generated. note that once set to a logic 1, the isr bit-4 will stay a logic 1 until xon character(s) are received. isr bit 6-7: (logic 0 or cleared is the default condition) these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled. line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr bit 0-1: (logic 0 or cleared is the default condi- tion) these two bits specify the word length to be transmit- ted or received. bit-1 bit-0 word length 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunction with the programmed word length. bit-2 word length stop bit length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2
st16c654/654d 5-93 rev. 4.10 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity. (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors. lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced. (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr lcr lcr parity selection bit-5 bit-4 bit-3 x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity 1 1 1 1 forced parity 0 lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled. (normal default condition) logic 1 = divisor latch and enhanced feature register enabled. modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force -rts output to a logic 1. (normal default condition) logic 1 = force -rts output to a logic 0. automatic rts may be used for hardware flow control by enabling efr bit-6 (see efr bit-6). mcr bit-2: this bit is used in the loopback mode only. in the loopback mode this bit is use to write the state of the modem -ri interface signal via -op1. mcr bit-3: ( used to control the modem -cd signal in the loopback mode.) logic 0 = forces int (a-d) outputs to the three state mode during the 16 mode. (normal default condition) in the loopback mode, sets -op2 (-cd) internally to a logic 1. logic 1 = forces the int (a-d) outputs to the active mode during the 16 mode. in the loopback mode, sets -op2 (-cd) internally to a logic 0. mcr bit-4: logic 0 = disable loopback mode. (normal default condition) logic 1 = enable local loopback mode (diagnostics).
st16c654/654d 5-94 rev. 4.10 mcr bit-5: logic 0 = disable xon any function (for 16c550 compatibility). (normal default condition) logic 1 = enable xon any function. in this mode any rx character received will enable xon. mcr bit-6: logic 0 = enable the standard modem receive and transmit input/output interface. (normal default condi- tion) logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ inputs are routed to the infrared encoder/decoder. the data input and output levels will conform to the irda infrared interface requirement. as such, while in this mode the infrared tx output will be a logic 0 during idle data conditions. mcr bit-7: logic 0 = divide by one. the input clock (crystal or external) is divided by sixteen and then presented to the programmable baud rate generator (bgr) with- out further modification, i.e., divide by one. (normal, default condition) logic 1 = divide by four. the divide by one clock described in mcr bit-7 equals a logic 0, is further divided by four (also see programmable baud rate generator section). line status register (lsr) this register provides the status of data transfers between. the 654 and the cpu. lsr bit-0: logic 0 = no data in receive holding register or fifo. (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when addi- tional data arrives while the fifo is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transfered into the fifo, therefore the data in the fifo is not corrupted by the error. lsr bit-2: logic 0 = no parity error. (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. lsr bit-3: logic 0 = no framing error. (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: logic 0 = no break condition. (normal default condi- tion) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr bit-5: this bit is the transmit holding register empty indi- cator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr bit-6: this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr bit-7: logic 0 = no error. (normal default condition) logic 1 = at least one parity error, framing error or
st16c654/654d 5-95 rev. 4.10 break indication is in the current fifo data. this bit is cleared when lsr register is read. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device that the 654 is connected to. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. msr bit-0: logic 0 = no -cts change (normal default condition) logic 1 = the -cts input to the 654 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no -dsr change. (normal default condition) logic 1 = the -dsr input to the 654 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no -ri change. (normal default condition) logic 1 = the -ri input to the 654 has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no -cd change. (normal default condition) logic 1 = indicates that the -cd input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: -cts functions as hardware flow control signal input if it is enabled via efr bit-7. the transmit holding register flow control is enabled/disabled by msr bit-4. flow control (when enabled) allows the starting and stopping the transmissions based on the external modem -cts signal. a logic 1 at the -cts pin will stop 654 transmissions as soon as current character has finished transmission. normally msr bit-4 bit is the compliment of the -cts input. however in the loopback mode, this bit is equivalent to the rts bit in the mcr register. msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the -dsr input. in the loopback mode, this bit is equivalent to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the -ri input. in the loopback mode this bit is equivalent to the op1 bit in the mcr register. msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the -cd input. in the loopback mode this bit is equivalent to the op2 bit in the mcr register. scratchpad register (spr) the st16c654 provides a temporary data register to store 8 bits of user information. enhanced feature register (efr) enhanced features are enabled or disabled using this register. bits-0 through 4 provide single or dual character software flow control selection. when the xon1 and xon2 and/or xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequen- tial characters. efr bit 0-3: (logic 0 or cleared is the default condi- tion) combinations of software flow control can be selected by programming these bits.
st16c654/654d 5-96 rev. 4.10 table 8, software flow control functions cont-3 cont-2 cont-1 cont-0 tx, rx software flow controls 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1011 transmit xon1/ xoff1. receiver compares xon1 and xon2, xoff1 and xoff2 0111 transmit xon2/xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 1111 transmit xon1 and xon2/xoff1 and xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 0011no transmit flow control receiver compares xon1 and xon2/xoff1 and xoff2 efr bit-4: enhanced function control bit. the content of the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 can be modified and latched. after modifying any bits in the enhanced registers, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents existing software from altering or overwriting the 654 enhanced functions. logic 0 = disable/latch enhanced features. ier bits 4- 7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings, then ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are initialized to the default values shown in the internal resister table. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c554 mode. (normal default condition). logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features of the 654 are enabled and user settings stored during a reset will be restored. efr bit-5: logic 0 = special character detect disabled. (normal default condition) logic 1 = special character detect enabled. the 654 compares each incoming receive character with xoff- 2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. bit-0 in the x-registers corresponds with the lsb bit for the receive character. when this feature is enabled, the normal software flow control must be disabled (efr bits 0-3 must be set to a logic 0). efr bit-6: automatic rts may be used for hardware flow control by enabling efr bit-6. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the programmed trigger level and -rts will go to a logic 1 at the next trigger level. -rts will return to a logic 0 when data is unloaded below the next lower trigger level (programmed trigger level -1). the state of this register bit changes with the status of the hardware flow control. -rts functions normally when
st16c654/654d 5-97 rev. 4.10 hardware flow control is disabled. 0 = automatic rts flow control is disabled. (normal default condition) 1 = enable automatic rts flow control. efr bit-7: automatic cts flow control. logic 0 = automatic cts flow control is disabled. (normal default condition) logic 1 = enable automatic cts flow control. trans- mission will stop when -cts goes to a logical 1. transmission will resume when the -cts pin returns to a logical 0. fifo ready register this register is applicable to 100 pin st16c654s only. the fifo resister provides the realtime status of the transmit and receive fifos. each tx and rx cannel (a-d) has its own 64 byte fifo. when any of the eight tx/rx fifos become full, a bit associated with its tx/ rx function and channel a-d is set in the fifo status register. fifo channel a-d rdy bit 0-3: 0 = the transmit fifo a-d associated with this bit is full. this channel will not accept any more transmit data. 1 = one or more empty locations exist in the fifo. fifordy bit 4-7: 0 = the receive fifo is above the programmed trigger level or time-out is occurred. 1 = receiver is ready and is below the programmed trigger level. st16c654 external reset conditions registers reset state ier ier bits 0-7=0 isr isr bit-0=1, isr bits 1-7=0 lcr lcr bits 0-7=0 mcr mcr bits 0-7=0 lsr lsr bits 0-4=0, lsr bits 5-6=1 lsr, bit 7=0 msr msr bits 0-3=0, msr bits 4-7= input signals fcr fcr bits 0-7=0 efr efr bits 0-7=0 signals reset state tx a-d high -rts a-d high -dtr a-d high -rxrdy a-d high -txrdy a-d low
st16c654/654d 5-98 rev. 4.10 t 1w, t 2w clock pulse duration 20 20 ns t 3w oscillator/clock frequency 8 24 mhz t 6s address setup time 10 5 ns t 7d -ior delay from chip select 10 10 ns t 7w -ior strobe width 50 25 ns t 7h chip select hold time from -ior 5 5 ns t 9d read cycle delay 50 50 ns t 12d delay from -ior to data 35 25 ns t 12h data disable time 35 35 35 ns t 13d -iow delay from chip select 10 10 ns t 13w -iow strobe width 40 40 ns t 13h chip select hold time from -iow 0 0 ns t 15d write cycle delay 50 50 ns t 16s data setup time 20 15 ns t 16h data hold time 50 35 ns t 17d delay from -iow to output 50 50 ns 100 pf load t 18d delay to set interrupt from modem 50 35 ns 100 pf load input t 19d delay to reset interrupt from -ior 50 35 ns 100 pf load t 20d delay from stop to set interrupt 1 rclk 1 rclk rclk t 21d delay from -ior to reset interrupt 200 200 ns 100 pf load t 22d delay from stop to interrupt 100 100 ns t 23d delay from initial int reset to transmit 8 24 8 24 rclk start t 24d delay from -iow to reset interrupt 175 175 ns t 25d delay from stop to set -rxrdy 1 1 rclk t 26d delay from -ior to reset -rxrdy 175 175 ns t 27d delay from -iow to set -txrdy 175 175 ns t 28d delay from start to reset -txrdy 8 8 rclk t 30s address setup time 10 10 ns t 30w chip select strobe width 40 40 ns t 30h address hold time 15 15 ns t 30d read cycle delay 70 70 ns t 31d delay from -cs to data 15 15 ns t 31h data disable time 15 ns t 32s write strobe setup time 10 10 ns t 32h write strobe hold time 10 10 ns t 32d write cycle delay 70 70 ns symbol parameter limits limits units conditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified.
st16c654/654d 5-99 rev. 4.10 t 33s data setup time 20 15 ns t 33h data hold time 10 10 ns t r reset pulse width 40 40 ns n baud rate devisor 1 2 16 -1 1 2 16 -1 rclk symbol parameter limits limits units conditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified.
st16c654/654d 5-100 rev. 4.10 symbol parameter limits limits units conditions 3.3 5.0 min max min max v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 m a i cl clock leakage 10 10 m a i cc avg power supply current 3 6 ma c p input capacitance 5 5 pf r in internal pull-up resistance 3 15 k w note: see the symbol description table, for a listing of pins having internal pull-up resistors. absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified.
st16c654/654d 5-101 rev. 4.10 general write timing in 68 mode general read timing in 68 mode a0-a4 -cs r/-w d0-d7 t30s t30h t30w t32s t32h t32d t33s t33h 8654-wd-1 -cs r/-w d0-d7 t30s t30h t31h t31d t30d t30w 8654-rd-1 a0-a4
st16c654/654d 5-102 rev. 4.10 general write timing in 16 mode general read timing in 16 mode a0-a2 -cs -iow d0-d7 t6s t13w t13d t13h t15d t16s t16h x654-wd-2 valid address active active data a0-a2 -cs -ior d0-d7 t6s t7w t7d t7h t9d t12d t12h x654-rd-2 active data valid address active
st16c654/654d 5-103 rev. 4.10 external clock timing modem input/output timing -iow -rts -dtr -cd -cts -dsr int -ior -ri t17d t18d t18d t19d t18d x654-md-1 active active change of state change of state active active active change of state change of state change of state active active t3w t1w t2w external clock x654-ck-1
st16c654/654d 5-104 rev. 4.10 receive timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rx next data start bit int -ior t20d t21d 16 baud rate clock x654-rx-1 active active
st16c654/654d 5-105 rev. 4.10 receive timing in fifo mode receive ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx first byte that reaches the trigger level -rxrdy -ior t25d t26d x654-rx-3 active data ready active stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx next data start bit -rxrdy -ior t25d t26d x654-rx-2 active data ready active
st16c654/654d 5-106 rev. 4.10 transmit timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx next data start bit int t22d t24d 16 baud rate clock x654-tx-1 -iow t23d active active tx ready active
st16c654/654d 5-107 rev. 4.10 transmit ready timing in none fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit tx next data start bit -txrdy t28d x654-tx-2 -iow t27d byte #1 active active transmitter ready transmitter not ready d0-d7
st16c654/654d 5-108 rev. 4.10 transmit ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx -iow d0-d7 -txrdy byte #64 t28d t27d x654-tx-3 fifo full active
st16c654/654d 5-109 rev. 4.10 infrared transmit timing infrared receive timing uart frame data bits start stop 0000 0 11 111 tx data irtx (a-d) tx bit time 1/2 bit time 3/16 bit time uart frame data bits start stop 0000 0 11 111 bit time 0-1 16x clock delay x654-ir-1 rx data irrx (a-d) rx
package dimensions 78 a 0.102 0.130 2.60 3.30 0.102 0.134 2.60 3.40 a 1 0.002 0.010 0.05 0.25 0.002 0.014 0.05 0.35 a 2 0.100 0.120 2.55 3.05 0.100 0.120 2.55 3.05 b 0.009 0.015 0.22 0.38 0.009 0.015 0.22 0.38 c 0.005 0.009 0.13 0.23 0.005 0.009 0.13 0.23 d 0.904 0.923 22.95 23.45 0.931 0.951 23.65 24.15 d 1 0.783 0.791 19.90 20.10 0.783 0.791 19.90 20.10 e 0.667 0.687 16.95 17.45 0.695 0.715 17.65 18.15 e 1 0.547 0.555 13.90 14.10 0.547 0.555 13.90 14.10 e 0.0256 bsc 0.65 bsc 0.0256 bsc 0.65 bsc l 0.029 0.040 0.73 1.03 0.026 0.037 0.65 0.95 a 0 7 0 7 0 7 0 7 100 lead plastic quad flat pack (14 mm x 20 mm, qfp) rev. 2.00 symbol min max min max inches millimeters 80 51 50 31 130 81 100 d d 1 e e 1 b e a 2 a a 1 a seating plane note: the control dimension is the millimeter column l c min max min max inches millimeters 1.6 mm form 1.95 mm form
package dimensions 86 a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.005 0.009 0.13 0.23 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d 1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 64 lead thin quad flat pack (10 x 10 x 1.4 mm, tqfp) rev. 2.00 symbol min max min max inches millimeters 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a a 1 a seating plane note: the control dimension is the millimeter column l c
package dimensions 38 68 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 d d 1 d 3 d 2 a a 1 268 a 0.165 0.200 4.19 5.08 a 1 0.090 0.130 2.29 3.30 a 2 0.020 . 0.51 b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.985 0.995 25.02 25.27 d 1 0.950 0.958 24.13 24.33 d 2 0.890 0.930 22.61 23.62 d 3 0.800 typ. 20.32 typ. e 0.050 bsc 1.27 bsc h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 symbol min max min max inches millimeters b a 2 b 1 e seating plane d 3 note: the control dimension is the inch column 45 x h2 45 x h1 c r
notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1994 exar corporation reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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